Phase locked loop (PLL) is a well known method of synchronizing a local voltage controlled oscillator to a reference frequency or some fraction or multiple of the reference frequency. PLL technology has been used widely since the very early days of the electronics age, and continues to be an important component of electronic products such as personal computers (PC)s, where the PLL's are used to synchronize components to a reference clock for the orderly and synchronized processing of data.
The basic building blocks of a PLL 100, shown in FIG. 1, include a phase detector 112, a loop filter 114 and the voltage controlled oscillator (VCO) 116. The phase detector 112 compares the phase difference between the incoming reference signal (FREF) 118 and the local signal (Fvco) 120 generated from the VCO 116. The phase error output signal 121 from the phase detector 112 is then fed through the loop filter 114 and back to adjust the VCO 116 until the phase error signal 121 is zero. For example, if the local signal from the VCO 120 is ahead of the reference input signal 118, the phase detector 112 will send out a negative phase error signal 121 to slow down the VCO 116 until the VCO output signal 120 is finally synchronized with the reference signal 118. If the VCO output signal 120 is behind the reference signal 118, the phase detector 112 will send out a positive phase error signal 121 to speed up the VCO 116 until it catches up with the reference signal 118. Eventually, the VCO 116 will be synchronized with the reference signal 118 all the time and it is said to be in the locked condition when the synchronization occurs.
It is common to use a phase detector 112 that can detect both the frequency error and the phase error and has only one stable operating point, usually called a digital phase frequency detector (PFD). Use of a PFD allows a VCO output signals that is initially far apart in frequency for the reference frequency, to be locked with the reference signal. A basic PFD 280 with charge pump output is shown in FIG. 2 and is comprising of a reference flip-flop 122, a VCO flip-flop 124 and an AND logic gate 126. The basic PFD 280 generates two outputs, one can be used to enable a sourcing charge pump to pump UP the frequency of VCO and the other one can be used to enable a sinking charge pump to suck DOWN the frequency of VCO.
Ideally the PLL 100 should operate so that when the two frequencies are synchronized, the PFD 280 with charge pump output will essentially do nothing. There is, however, a well-known problem with the PFD 280 with charge pump output called the “dead-zone” problem. The causes of this problem are discussed in detail later. The dead-zone problem manifests itself as the VCO exhibiting significant jitter if the signals to the PFD 280 with charge pump output are exactly synchronized. The workaround used in practice is to avoid the dead-zone by introducing delays into the reset path of the PFD 280 with charge pump output that slow down or stretch the time period of the flip-flop reset time. The problem with this approach is that the clock rates that can be synchronized are only a fraction of the maximum switching speed of the flip-flop.
For example, a typical self-toggling flip-flop constructed using 0.35 micron line-width silicon fabrication technology can toggle at around 800 MHz. The maximum operation speed of a PFD using this flip-flop is, however, limited to less than 400 MHz because of the delays introduced to avoid the dead-zone. PC clock speeds are approaching the speeds when these dead-zone workarounds cause problems or require switching to more expensive fabrication techniques.
And worst of all, the dead-zone problem is only avoided but not solved so that there is always a chance that the PFD may step into the dead-zone and cause a jittering problem. The dead-zone jittering problem is especially critical for PC clock application where the PC system is orderly operated according to each edge of the clock. A single clock jitter can cause a command or data to be executed wrongly and the PC will never be able to recover from the mistake and crash.
What is needed is a method of detecting phase and frequency differences that does not require introducing artificial delays so that higher clock rates can be synchronized using PFD made using existing, inexpensive fabrication protocols and also solves the dead-zone jittering problem once and for all so that the dead-zone jittering problem is completely eliminated and is not allowed to occur.